1. Field of the Invention
This invention relates in general to the design and method of manufacture of packages for semiconductor chips, and the input, output (I/O), interconnections to the chips, and more specifically to a semiconductor package that incorporates a molding compound to encapsulate the semiconductor chip and allows the semiconductor chip to be interconnected to other devices without the use of a first level package or interposer.
2. Description of the Related Art
The following three U.S. patents and one U.S. patent application relate to semiconductor chip packaging designs.
U.S. Pat No. 5,596,227 issued Jan. 21, 1997, to H. Saito discloses a semiconductor chip wire bonded and molded to a printed circuit interposer containing BGA interconnects.
U.S. Pat. No. 5,969,426 issued Oct. 19, 1997, to S. Baba et. al. describes a semiconductor chip flip-chip bonded and molded on a printed circuit substrate containing BGA interconnects.
U.S. Pat. No. 6,166,433 issued Dec. 26, 2000, to A. Takashirna et. al. shows a semiconductor chip bonded on a FPC tape that contains a BGA.
U.S. Pat. Application Publication, U.S. 2002/0033412A1, published Mar. 21, 2002, by F. Tung describes the use of Cu copper pillars on semiconductor chips, and is assigned to the same assignee as the instant invention.
The advent of VLSI technology in the semiconductor field has resulted in the demand for high-density packaging. Semiconductor packaging traditionally has three levels of package. The first level, a single chip module (SCM) is made up of a semiconductor chip attached to a substrate. A substrate and chip assembly is usually molded in an encapsulant for environmental protection. The second level of package, usually a printed circuit card, mounts and interconnects the single chip modules and has a connector system to the third level package, usually a planar printed circuit board.
Elimination of a level of package has been a driving force in electronic system design in the recent past. This reduction in packaging levels would allow for closer spacing of semiconductor chips thereby reducing signal delay times. One design currently in use is direct chip attach (DCA). In this design chips are flip-chip mounted onto a substrate, usually ceramic, and the assembly sealed in an enclosure for environmental protection. The environmental protection is required to protect the semiconductor and interconnections against corrosive elements and mechanical disturbances. The inclusion of enclosures for environmental protection results in larger packages with larger distances between semiconductor chips and thereby longer signal delays.
Several interconnection technologies have been developed for use in DCA designs. TAB tape utilizes the periphery of the semiconductor chip as does fine pitch surface mount (FPT). Inherent in these designs is that the peripheral leads increase the space required by each semiconductor chip. Again this increase in chip spacing results in longer signal delays.
The ball grid array (BGA) technology is an area array interconnect design, wherein the front surface of the semiconductor chip is utilized for an array of solder spheres used to interconnect to the next level of package. This arrangement allows for the interconnects to remain within the area of the semiconductor chip.
As dimensions of semiconductor devices became smaller an additional demand on semiconductor chip interconnects has emerged. Alpha particles emitted from solder alloys have been shown to cause semiconductor devices to malfunction. Interconnections that contain solder alloys need to be physically spaced away from the semiconductor devices. One design approach is to include copper pillars on the surface of the semiconductor chips. This approach is disclosed in U.S. Patent Application Publication U.S. 2002/0033412A1 dated Mar. 21, 2002. The copper pillars are incorporated between the solder of the BGA and the surface of the semiconductor chip so as to reduce the effect of the alpha particles on the devices.
First level package designs need to address the following:
Allow for reliable interconnections to the chip surface and to the next level of package.
Protect the chip and the interconnects from chemical corrosion.
Protect the chip from physical and mechanical disturbances, (shock and vibrations.)
A present design that has been shown to be capable of addressing the above demands is shown in FIG. 1 (Prior Art). A semiconductor chip 10 that has a BGA 12 on the front surface is bonded onto an interposer 14 that has printed metallurgy to connect the chip I/Os to peripheral TAB connections 16. The assembly is encapsulated in a plastic compound 18 for environmental protection. Although this design satisfies the criteria set above it has the disadvantage of increasing the area required by the semiconductor chip by 4xxcx9c9x, due to the use of the interposer.
The main objective of the invention is to provide a package design for semiconductor chips that eliminates the need for a first level package. The package design should provide reliable interconnections to the chip and to the next level of package. In addition it needs to protect the semiconductor chip and the interconnections from the environment.
Another objective is for the invention to provide a method for manufacturing the semiconductor chip package in a reliable and efficient manner.
An additional objective is for the package to have a minimal impact on increasing the area required by the semiconductor chip.
The above objectives are achieved by the present invention by providing a design and method of manufacture for a semiconductor chip grid array (CGA) package.
An embodiment of the present invention is shown in FIG. 2B. The semiconductor chip 20 with conductive pillars 22 is fully encapsulated in a molding compound 26 that incorporates castellations 28 for better electrical isolation of the interconnects. A bottom view is shown in FIG. 2A. The package has a fully encapsulated or molded semiconductor chip and provides a CGA for interconnect to the next level of package while eliminating the need for a substrate or interposer.
A manufacturing method for the semiconductor CGA package utilizes a copper lead frame tape that carries the semiconductor chips. The semiconductor chips include solderable pillars. The tape with the semiconductor chips mounted progresses through a molding process that forms a molded panel of a quantity of chips. The units are then separated from the tape and solder balls are mounted on the pillars. The units may be tested at this stage. The molded semiconductor CGA assemblies are then separated into single chip modules.